In relation to data transfer devices such as DMA (Direct Memory Access), various techniques have been proposed to improve data transfer efficiency. For example, Patent Literature (PTL) 1 discloses a DMA controller which alternately controls a first count control unit to control a transfer parameter for a first DMA transfer channel and a second count control unit to control a transfer parameter for a second DMA transfer channel. While a data transfer of a plurality of data blocks is in progress, the second count control unit loads from the memory a transfer parameter for the data block to be transferred subsequently, during an idle cycle in a data transfer by the first count control unit. In this way, the DMA controller disclosed in PTL 1 intends to eliminate the need for control by a CPU and to cancel a delay between a completion time of a data block transfer and an activation time of the subsequent data block transfer.
In addition, PTL 2 aims to reduce load on a CPU, and discloses that the need for interruption to a CPU, which may otherwise occur for each DMA transfer, is eliminated in such a manner that address information of a transfer parameter of a DMA in a main storage device is stored in an address register, and a transfer parameter is read according to the address information stored in the address register, and registered in a parameter register.
PTL 3 discloses a device provided with a first processor and a second processor and designed to achieve efficient use of the first processor and the second processor. In the device, the first processor writes into a memory data transfer information including information indicating a storage location in a first storage area and information indicating a storage location in a second storage area, and then the second processor reads the data transfer information from the memory, and transfers to the second storage area the data stored in the first storage area, according to the data transfer information. In this manner, the first processor is enabled to start execution of subsequent processing without waiting for a notification from the second processor.